* At least one year of design experience in digital logic design, FPGA prototyping, or a related area.
* Proficiency in SystemVerilog and Verilog.
* Strong analytical and problem-solving skills.
* Very good written and oral communication skills in English.
* Ability to work independently and manage multiple tasks.
* Excellent teamwork abilities and a proactive attitude.
* Knowledge of SDC (Synopsys Design Constraints) is a plus.
* Experience in functional verification and/or UVM (Universal Verification Methodology) is a plus
